1. Field
Various features relate to integrated devices, and more particularly to integrated device packages having embedded package substrate capacitors with configurable/controllable equivalent series resistance.
2. Background
Modern electronic devices, such as mobile phones, laptop computers, tablets computer devices, etc., often include multiple integrated circuits (ICs) and subsystems on a substrate, and/or a printed circuit board (PCB). For example, a PCB, such as a “motherboard,” may include an “applications processor” responsible for executing much of the calculation intensive processes associated with running applications for the electronic device. Another IC, for example a power management integrated circuit (PMIC), may be responsible for providing power (e.g., one or more supply voltages and currents) from a battery to the applications processor and other ICs of the electronic device. The network of passive and active circuit components, such as wires, traces, vias, other conductive components, capacitors, and/or inductors that ultimately deliver the supply voltages and currents from the PMIC to another IC of the electronic device, such as the applications processor, may be collectively known as the “power delivery network.”
The power delivery network (PDN) has losses associated with it due to resistance and other parasitic capacitive and inductive components. Thus, the PDN has an impedance associated with it that varies according to frequency. Minimizing this impedance is imperative for power conservation and energy efficiency of the electronic device. One way to reduce this impedance is to use monolithic ceramic capacitors, or decoupling capacitors, for eliminating noise and absorbing load fluctuations during operation.
Decoupling capacitors have a controlled capacitance, a constant intrinsic equivalent series inductance (ESL), and an equivalent series resistance (ESR). The capacitance and ESL of a decoupling capacitor (or network of capacitors) are used to reduce the power delivery network impedance in a particular frequency range. The ESR of a capacitor determines the amount by which the power delivery network impedance is reduced and the frequency range where this occurs. In general, the lower the ESR, the more limited the frequency band in which the capacitor is effective in lowering impedance. Although ESR-controlled capacitors are very useful in suppressing PDN resonance, ESR-controlled embedded package substrate (EPS) capacitors are not available.
FIG. 1 illustrates a cross-sectional view of a conventional packaging substrate 100. As shown, the packaging substrate 100 includes a substrate 102, having a dielectric layer 104 and several conductive layers 106-112, for example, and one or more embedded package substrate (EPS) capacitors 114, 116. The EPS capacitors 114, 116 are coupled to a first set of vias 118a-b, 120a-b, respectively, and a second set of vias 122a-b, 124a-b, respectively. FIG. 2 illustrates a cross sectional view of one of the EPS capacitors 114 or 116 of FIG. 1. The EPS capacitors 114, 116 of the prior art lack equivalent series resistance (ESR) control and thus the ability to reduce resonance frequency in the PDN.
FIG. 3 illustrates a cross sectional view of a conventional capacitor 300 modified to add an ESR control feature. As shown, the capacitor includes a pair of external electrodes 302 and a plurality of internal electrodes 304. A high resistance material 306 has been added to one side of the capacitor 306 which forms an ESR control feature. As only one side of the capacitor 300 has a high resistance variable, this modified capacitor is only compatible with surface mount technology (SMT). As such, these modified capacitors can only be mounted or placed directly onto the surface of integrated device packages or printed circuit boards.
FIGS. 4 (comprising FIGS. 4A-4C) and 5 illustrate a general concept of typical two-terminal multilayer ceramic capacitor as well as a prior art approach for controlling ESR in a multi-layered ceramic capacitor (MLCC). The formation of first and second plates of a conventional, prior art, two-terminal multilayer ceramic capacitor is shown in FIGS. 4A, 4B and 4C. FIG. 4A is an illustration of one layer within the multilayer structure with an electrode plate 402 that extends to one edge 404, with a margin along the remaining three edges. The edge 404 is exposed and utilized as an electrical contact to the plate 402, once the capacitor is assembled. In FIG. 4B, the adjacent layer shows the electrode plate 406 extending to the edge 408 that is opposite of the previous termination edge 404. FIG. 4C shows how these plates overlap and create an effective area 410 with margins along all edges. The termination edges for plate 404 extend from the effective area 410 to the left edge 404, while the termination edges for plate 406 are shown to extend to the right edge 408. A termination paste (412 and 414) is applied to cover these edges and connect all like terminated plates together. The over-wrap of the termination paste (412 and 414) along the bottom of the chip, affords metallic strips extending from the face of the ceramic that are utilized to solder mount this capacitor to the circuit board. These terminations (412 and 414) create the two contacts for this two-terminal device.
FIG. 5 illustrates another prior art approach for controlling ESR in a multi-layered ceramic capacitor (MLCC) by altering the geometry of the inner and outer electrodes of the capacitor. FIG. 6 illustrates a perspective view and a top view of the MLCC of FIG. 5 while FIG. 7 illustrates the capacitor pattern and ESR pattern of the MLCC of FIG. 5. In this approach, the ESR of an MLCC is decided by the number of inner electrodes connected to the outer termination. With this MLCC design, the inner electrodes which are not connected to outer termination will be common through the no contact (NC) terminal. The NC terminal is not connected electrically to the circuit on the PCB. Even though the number of inner electrodes connecting to the outer termination is reduced, the capacitance value will still depend on the total number of inner electrodes. Although the MLCC as shown in FIGS. 5-7 allow for the arbitrary setting of the ESR value by changing the conductor resistance of the layers based on a combination of multiple internal electrode patterns, the MLCC also can only mounted or placed directly onto the surface of integrated circuit packages or printed circuit boards printed circuit boards.
In view of the above, there is a need for a design that provides a capacitor having an ESR control feature implemented or embedded in the substrate level of integrated device packages or printed circuit boards printed circuit boards for optimal PDN performance.